View AMIS42665TJAA6RG_4408944.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2010 november, 2010 ? rev. 9 1 publication order number: amis ? 42665/d amis-42665 high-speed low power can transceiver description the amis ? 42665 can transceiver is the interface between a controller area network (can) protocol controller and the physical bus and may be used in both 12 v and 24 v systems. the transceiver provides differential transmit capability to the bus and differential receive capability to the can controller. due to the wide common ? mode voltage range of the receiver inputs, the amis ? 42665 is able to reach outstanding levels of electromagnetic susceptibility (ems). similarly, extremely low electromagnetic emission (eme) is achieved by the excellent matching of the output signals. the amis ? 42665 is a new addition to the can high ? speed transceiver family and offers the following additional features: features ? wake ? up (wu) over bus ? voltage source via v split pin for stabilizing the recessive bus level (further emc improvement) ? ideal passive behavior when supply voltage is removed ? extremely low current standby mode ? compatible with the iso 1 1898 standard (iso 11898 ? 2, iso 11898 ? 5 and sae j2284) ? high speed (up to 1 mbps) ? ideally suited for 12 v and 24 v industrial and automotive applications ? extremely low current standby mode with wake ? up via the bus ? low eme common ? mode choke is no longer required ? differential receiver with wide common ? mode range ( 35 v) for high ems ? transmit data (txd) dominant time ? out function ? thermal protection ? bus pins protected against transients in an automotive environment ? power down mode in which the transmitter is disabled ? bus and v split pins short circuit proof to supply voltage and ground ? logic level inputs compatible with 3.3 v devices ? these are pb ? free devices http://onsemi.com (top view) 5 6 7 8 1 2 3 4 txd rxd stb gnd canl canh amis ? 42665 pc20040829.1 see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information v cc v split 1 8 xxxxx alyw 1 8 xxxxx = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package marking diagram soic ? 8 case 751 pin assignment
amis ? 42665 http://onsemi.com 2 table 1. technical characteristics symbol parameter conditions min max unit v cc power supply voltage 4.75 5.25 v v stb dc voltage at pin stb ? 0.3 v cc v v txd dc voltage at pin txd ? 0.3 v cc v v rxd dc voltage at pin rxd ? 0.3 v cc v v canh dc voltage at pin canh 0 < v cc < 5.25 v; no time limit ? 35 +35 v v canl dc voltage at pin canl 0 < v cc < 5.25 v; no time limit ? 35 +35 v v split dc voltage at pin v split 0 < v cc < 5.25 v; no time limit ? 35 +35 v v o(dif)(bus_dom) differential bus output voltage in dominant state 42.5 < r lt < 60 1.5 3 v cm ? range input common ? mode range for comparator guaranteed differential receiver threshold and leakage current ? 35 +35 v v cm ? peak common ? mode peak see figures 11 and 12 ? 500 500 mv c load load capacitance on ic outputs 10 pf t pd(rec ? dom) propagation delay txd to rxd see figure 7 90 230 ns t pd(dom ? rec) propagation delay txd to rxd see figure 7 90 245 ns t j junction temperature ? 40 150 c vsplit mode & wake ? up control wake ? up filter amis ? 42665 stb gnd rxd vcc 2 3 7 6 comp comp 5 timer vcc txd 1 driver control thermal shutdown vcc 8 4 vsplit vcc pc20050211.1 por canh canl figure 1. block diagram + ? + ?
amis ? 42665 http://onsemi.com 3 typical application amis ? 42665 vcc stb rxd txd 1 4 can controller gnd vcc vbat in out gnd 2 3 8 canh canl vsplit 5 6 7 can bus pc20040829.3 r figure 2. application diagram 5v ? reg c lt = 47 nf r lt = 60 table 2. pin list and descriptions pin name description 1 txd transmit data input; low input dominant driver; internal pullup current 2 gnd ground 3 v cc supply voltage 4 rxd receive data output; dominant transmitter low output 5 v split common ? mode stabilization output 6 canl low ? level can bus line (low in dominant mode) 7 canh high ? level can bus line (high in dominant mode) 8 stb standby mode control input
amis ? 42665 http://onsemi.com 4 table 3. absolute maximum ratings symbol parameter conditions min. max. unit v cc supply voltage ? 0.3 +7 v v canh dc voltage at pin canh 0 < v cc < 5.25 v; no time limit ? 50 +50 v v canl dc voltage at pin canl 0 < v cc < 5.25 v; no time limit ? 50 +50 v v split dc voltage at pin v split 0 < v cc < 5.25 v; no time limit ? 50 +50 v v txd dc voltage at pin txd ? 0.3 v cc + 0.3 v v rxd dc voltage at pin rxd ? 0.3 v cc + 0.3 v v stb dc voltage at pin stb ? 0.3 v cc + 0.3 v v tran(canh) transient voltage at pin canh note 1 ? 300 +300 v v tran(canl) transient voltage at pin canl note 1 ? 300 +300 v v tran(vsplit) transient voltage at pin v split note 1 ? 300 +300 v v esd(canl/ canh/vsplit) electrostatic discharge voltage at canh and canl pin note 2 note 4 ? 8 ? 500 +8 +500 kv v v esd electrostatic discharge voltage at all other pins note 2 note 4 ? 5 ? 500 +5 +500 kv v latch ? up static latch ? up at all pins note 3 120 ma t stg storage temperature ? 55 +150 c t amb ambient temperature ? 40 +125 c t j maximum junction temperature ? 40 +170 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. applied transient waveforms in accordance with iso 7637 part 3, test pulses 1, 2, 3a, and 3b (see figure 5). 2. standardized human body model electrostatic discharge (esd) pulses in accordance to mil883 method 3015.7. 3. static latch ? up immunity: static latch ? up protection level when tested according to eia/jesd78. 4. standardized charged device model esd pulses when tested according to eos/esd ds5.3 ? 1993. table 4. thermal characteristics symbol parameter conditions value unit r th(vj ? a) thermal resistance from junction ? to ? ambient in soic ? 8 package in free air 145 k/w r th(vj ? s) thermal resistance from junction ? to ? substrate of bare die in free air 45 k/w functional description amis ? 42665 provides two modes of operation as illustrated in table 5. these modes are selectable through pin stb. table 5. operating modes mode pin stb pin rxd low high normal low bus dominant bus recessive standby high wake ? up request detected no wake ? up request detected normal mode in the normal mode, the transceiver is able to communicate via the bus lines. the signals are transmitted and received to the can controller via the pins txd and rxd. the slopes on the bus lines outputs are optimized to give extremely low eme. standby mode in standby mode both the transmitter and receiver are disabled and a very low ? power differential receiver monitors the bus lines for can bus activity. the bus lines are terminated to ground and supply current is reduced to a minimum, typically 10 a. when a wake ? up request is
amis ? 42665 http://onsemi.com 5 detected by the low ? power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of t dbus , the rxd pin is driven low by the transceiver to inform the controller of the wake ? up request. split circuit the v split pin is operational only in normal mode. in standby mode this pin is floating. the v split is connected as shown in figure 2 and its purpose is to provide a stabilized dc voltage of 0.5 x v cc to the bus avoiding possible steps in the common ? mode signal therefore reducing eme. these unwanted steps could be caused by an unpowered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal 0.5 x v cc voltage. wake ? up when a valid wake ? up (dominant state longer than t dbus ) is received during the standby mode the rxd pin is driven low. wake ? up behavior in case of a permanent dominant ? due to, for example, a bus short ? represents the only difference between the circuit sub ? versions listed in the ordering information table. it is depicted in figures 3 and 4. when the standby mode is entered while a dominant is present on the bus, the ?unconditioned bus wake ? up? versions will signal a bus ? wakeup immediately after the state transition (seen as a high ? level glitch on rxd). the other version (differing purely by a metal ? level modification in the digital part) will signal bus ? wakeup only after the initial dominant is released. in this way it? s ensured, that a can bus can be put to a low ? power mode even if the nodes have a level sensitivity to rxd pin and a permanent dominant is present on the bus. overtemperature detection a thermal protection circuit protects the ic from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 160 c. because the transmitter dissipates most of the power, the power dissipation and temperature of the ic is reduced. all other ic functions continue to operate. the transmitter off ? state resets when pin txd goes high. the thermal protection circuit is particularly needed when a bus line short circuits. txd dominant time ? out function a txd dominant time ? out timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication) if pin txd is forced permanently low by a hardware and/or software application failure. the timer is triggered by a negative edge on pin txd. if the duration of the low ? level on pin txd exceeds the internal timer value t dom(txd) , the transmitter is disabled, driving the bus into a recessive state. the timer is reset by a positive edge on pin txd. see figure 10. this txd dominant time ? out time (t dom(txd) ) defines the minimum possible bit rate to 40 kbps. fail safe features a current ? limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. the pins canh and canl are protected from automotive electrical transients (according to iso 7637; see figure 5). pins txd and stb are pulled high internally should the input become disconnected. pins txd, stb and rxd will be floating, preventing reverse supply should the v cc supply be removed. canh canl stb rxd normal standby* unconditioned wu figure 3. amis42665tjaa1/3 wake ? up behavior time t dbus t dbus *even if bus dominant signals longer than tdbus are echoed on rxd, the transceiver stays in standby mode until stb is released. figure 4. amis42665tjaa6 wake ? up behavior canh canl stb rxd normal standby* time *on this derivative, bus dominant signals longer than t dbus are echoed on rxd after the bus passed through a recessive time following the trigtger of stb. the transceiver stays in standby mode until stb is released. t dbus
amis ? 42665 http://onsemi.com 6 electrical characteristics definitions all voltages are referenced to gnd (pin 2). positive currents flow into the ic. sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. characteristics v cc = 4.75 v to 5.25 v; t j = ? 40 c to +150 c; r lt = 60 unless specified otherwise. symbol parameter conditions min typ max unit supply (pin v cc ) i cc supply current dominant; v txd = 0 v recessive; v txd = v cc 45 4 65 8 ma i ccs supply current in standby mode t j,max = 100 c 10 15 a transmitter data input (pin txd) v ih high ? level input voltage output recessive 2.0 ? v cc + 0.3 v v il low ? level input voltage output dominant ? 0.3 ? +0.8 v i ih high ? level input current v txd = v cc ? 5 0 +5 a i il low ? level input current v txd = 0 v ? 75 ? 200 ? 350 a c i input capacitance not tested ? 5 10 pf transmitter mode select (pin stb) v ih high ? level input voltage standby mode 2.0 ? v cc + 0.3 v v il low ? level input voltage normal mode ? 0.3 ? +0.8 v i ih high ? level input current v stb = v cc ? 5 0 +5 a i il low ? level input current v stb = 0 v ? 1 ? 4 ? 10 a c i input capacitance not tested ? 5 10 pf receiver data output (pin rxd) i oh high ? level output current v o = 0.7 x v cc ? 5 ? 10 ? 15 ma i ol low ? level output current v o = 0.3 x v cc 5 10 15 ma bus lines (pins canh and canl) v o(reces) (norm) recessive bus voltage normal mode v txd = v cc ; no load 2.0 2.5 3.0 v v o(reces) (stby) recessive bus voltage v txd = v cc ; no load standby mode ? 100 0 100 mv i o(reces) (canh) recessive output current at pin canh ? 35 v < v canh < +35 v; 0 v < v cc < 5.25 v ? 2.5 ? +2.5 ma i o(reces) (canl) recessive output current at pin canl ? 35 v < v canl < +35 v; 0 v < v cc < 5.25 v ? 2.5 ? +2.5 ma i li(canh) input leakage current to pin canh v cc = 0 v; v canl = v canh = 5 v ? 10 ? +10 a i li(canl) input leakage current to pin canl v cc = 0 v; v canl = v canh = 5 v ? 10 ? +10 a v o(dom) (canh) dominant output voltage at pin canh v txd = 0 v 3.0 3.6 4.25 v v o(dom) (canl) dominant output voltage at pin canl v txd = 0 v 0. 5 1.4 1.75 v v o(dif) (bus_dom) differential bus output voltage (v canh ? v canl ) v txd = 0 v; dominant; 42.5 < r lt < 60 1.5 2.25 3.0 v v o(dif) (bus_rec) differential bus output voltage (v canh ? v canl ) v txd = v cc ; recessive; no load ? 120 0 +50 mv i o(sc) (canh) short circuit output current at pin canh v canh = 0 v; v txd = 0 v ? 45 ? 70 ? 120 ma
amis ? 42665 http://onsemi.com 7 characteristics v cc = 4.75 v to 5.25 v; t j = ? 40 c to +150 c; r lt = 60 unless specified otherwise. symbol unit max typ min conditions parameter bus lines (pins canh and canl) i o(sc) (canl) short circuit output current at pin canl v canl = 36 v; v txd = 0 v 45 70 120 ma v i(dif) (th) differential receiver threshold voltage (see figure 6) ? 5 v < v canl < +12 v; ? 5 v < v canh < +12 v; 0.5 0.7 0.9 v v ihcm(dif) (th) differential receiver threshold voltage for high common ? mode (see figure 6) ? 35 v < v canl < +35 v; ? 35 v < v canh < +35 v; 0.40 0.7 1.00 v v i(dif) (hys) differential receiver input voltage hysteresis (see figure 6) ? 35 v < v canl < +35 v; ? 35 v < v canh < +35 v; 50 70 100 mv r i(cm) (canh) common ? mode input resistance at pin canh 15 26 37 k r i(cm) (canl) common ? mode input resistance at pin canl 15 26 37 k r i(cm) (m) matching between pin canh and pin canl common mode input resistance v canh = v canl ? 3 0 +3 % r i(dif) differential input resistance 25 50 75 k c i(canh) input capacitance at pin canh v txd = v cc ; not tested 7.5 20 pf c i(canl) input capacitance at pin canl v txd = v cc ; not tested 7.5 20 pf c i(dif) differential input capacitance v txd = v cc ; not tested 3.75 10 pf common ? mode stabilization (pin v split ) v split reference output voltage at pin v split normal mode; ? 500 a < i split < 500 a 0.3 x v cc ? 0.7 x v cc i split(i) v split leakage current standby mode ? 5 +5 a i split(lim) v split limitation current normal mode ? 3 +3 ma power ? on ? reset (por) porl por level canh, canl in tri ? state below por level 2.2 3.5 4.5 v thermal shutdown t j(sd) shutdown junction temperature 150 160 180 c timing characteristics (see figures 7 and 8) t d(txd ? buson) delay txd to bus active c l = 100 pf between canh to canl 40 85 105 ns t d(txd ? busoff) delay txd to bus inactive c l = 100 pf between canh to canl 30 60 105 ns t d(buson ? rxd) delay bus active to rxd c rxd = 15 pf 25 55 105 ns t d(busoff ? rxd) delay bus inactive to rxd c rxd = 15 pf 40 100 105 ns t pd(rec ? dom) propagation delay txd to rxd from recessive ? to ? dominant c l = 100 pf between canh to canl 90 230 ns t d(dom ? rec) propagation delay txd to rxd from dominant ? to ? recessive c l = 100 pf between canh to canl 90 245 ns t d(stb ? nm) delay standby mode to normal mode 5 7.5 10 s t dbus dominant time for wake ? up via bus 0.75 2.5 5 s t dom(txd) txd dominant time for time out v txd = 0 v 300 650 1000 s baudrate communication speed achievable 40k 1m bps
amis ? 42665 http://onsemi.com 8 measurement setups and definitions amis ? 42665 vcc gnd 2 3 canh canl vsplit 5 6 7 pc20040829.5 stb 8 rxd 4 txd 1 1 nf 100 nf +5 v 15 pf 1 nf transient generator figure 5. test circuit for automotive transients vrxd high low 0.5 0.9 pc20040829.7 hysteresis figure 6. hysteresis of the receiver v i(dif)(hys) amis ? 42665 vcc gnd 2 3 canh canl vsplit 5 6 7 rlt pc20040829.4 stb 8 rxd 4 txd 1 100 pf 100 nf +5 v 15 pf figure 7. : test circuit for timing characteristics clt 60
amis ? 42665 http://onsemi.com 9 canh canl txd dominant 0.9 v 0.5 v recessive 0.7 x vcc pc20040829.6 high low figure 8. timing diagram for ac characteristics 0.3 x vcc rxd t d(txd ? buson) t pd(rec ? dom) t d(busoff ? rxd) t d(txd ? busoff) t pd(dom ? rec) v i(dif) = v canh ? v canl mode normal standby transition delay stb t d(stb ? nm) time figure 9. transition from standby to normal figure 10. amis ? 42665 txd time ? out bus blockage prevention in case of controller failure txd canh canl t d(stb ? nm) time time ? out(*) *the time ? out is reset on txd rising edge.
amis ? 42665 http://onsemi.com 10 10 nf amis ? 42665 vcc gnd 2 3 canh canl vsplit 5 6 7 pc20040829.9 stb 8 rxd 4 txd 1 active probe 100 nf +5 v 15 pf generator 47 nf spectrum anayzer figure 11. basic test setup for electromagnetic measurement 30 30 6.2 k 6.2 k figure 12. eme measurements device ordering information part number version temperature range package type shipping ? amis42665tjaa1g unconditioned bus wake ? up ? 40 c ? 125 c soic ? 8* (pb ? free) 96 tube / tray amis42665tjaa1rg ? 40 c ? 125 c soic ? 8* (pb ? free) 3000 / tape & reel amis42665tjaa3l ? 40 c ? 125 c soic ? 8** (pb ? free) 96 tube / tray amis42665tjaa3rl ? 40 c ? 125 c soic ? 8** (pb ? free) 3000 / tape & reel amis42665tjaa6g bus wake ? up inactive in case of bus fault ? 40 c ? 125 c soic ? 8* (pb ? free) 96 tube / tray AMIS42665TJAA6RG ? 40 c ? 125 c soic ? 8* (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *matte sn, jedec ms ? 012 ** nipdau, jedec ms ? 012
amis ? 42665 http://onsemi.com 11 package dimensions soic ? 8 case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 amis ? 42665/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of AMIS42665TJAA6RG

	To Download AMIS42665TJAA6RG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .